1. Field of the Invention
The present invention relates to a structure of a substrate mostly used in an interposer of a semiconductor device and a process for manufacturing the substrate.
2. Description of the Related Art
In recent years, a semiconductor chip is increasingly miniaturized. Along with the miniaturization is increasingly adopted, in view of a cost efficiency, a mounting structure wherein, first, a semiconductor device is mounted on an interposer substrate which fills in a connection pitch difference between a mother board having a relatively low mounting density and a semiconductor chip to obtain a CSP (chip size package) and the CSP is then mounted on the mother board.
A build-up substrate was so far frequently used as the interposer substrate. As the technology has advanced in recent years, line/space pitches of wiring in the build-up substrate have reduced to such a fine dimension as approximately 10 microns; however, pitches of vias provided for connection in a thickness direction of the substrate are 100 microns at the very most. This is a serious bottleneck in the miniaturization of an interposer substrate.
Therefore, novel interposer substrates, which are not bound by the conventional concept of a build-up substrate, start being devised, as exemplified by those recited in No. 2003-152133 of the Japanese Patent Applications Laid-Open (hereinafter, referred to as conventional example 1). The conventional example 1 discloses an interposer substrate 200 in which wires are used. An outline of the interposer substrate 200 is described referring to FIG. 9. The interpose substrate 200 comprises a double-surfaced wiring board 100 and an insulation resin layer 141. In the double-surfaced wiring board 100, a land 121 and a terminal 122 for solder bump are electrically connected to each other through a via hole 131. The insulation resin layer 141 is formed on the double-surfaced wiring board 100. An electrical conduction lead 151a is extended from the land 121 in the insulation resin layer 141 toward a surface of the insulation resin layer 141. A connection terminal 151b is formed at the distal end of the electrical conduction lead 151a. 
An example of a manufacturing process of the interposer substrate 200 is described below. A double-surfaced wiring board 100, wherein the land 121 and the terminal 122 for solder bump are formed on both surfaces of an insulation substrate 111, is prepared. A wire 151a is extended from the land 121 of the double-surfaced wiring board 100 at a predetermined angle, and an insulation resin layer 141 is then formed. After the formation of the insulation resin layer 141, the wire 151a present on a surface of the insulation resin layer 141 is cut away, and the surface is polished. As a result, an interposer substrate (substrate for semiconductor package) 200, wherein the electrical conduction lead 151a is formed in the insulation resin layer 141 and the connection terminal 151b is formed on the surface of the insulation resin layer 141, is obtained.
In the conventional example 1 wherein the double-surfaced wiring board 100 is used, however, an inter-land interval is approximately 300 microns at the very most, which fails to meet the level of the miniaturization currently demanded. The conventional example 1 is further disadvantageous in that any effective measures for heat release and denoising, which are requirements of an interposer substrate in addition to miniaturization, have not been adopted.